1. Cross-Reference to Related Application
U.S. patent application entitled "Microwave Measurement System And Associated Method", invented by Martin I. Grace et al, filed on the same date as the present application, and owned currently and at the time of invention by a common assignee, is incorporated by reference.
2. Field of the Invention
The present invention relates to dividers in general and in particular to a dual modulus fractional divider for use in phase-locked loops which have an output frequency above 80 mHz, a resolution of 100 kHz or better and a loop band width of at least 100 kHz.
3. Description of the Prior Art
A typical phase-locked loop comprises a voltage controlled oscillator (VCO), a divider for dividing the output of the VCO, a phase detector, a reference oscillator having a fixed output frequency and a loop filter.
In operation, the frequency of the output signal from the VCO is divided by the divider and compared with the fixed frequency/phase of the output of the reference oscillator. If the frequency/phase of the output signal from the divider differs from the frequency/phase of the output of the reference oscillator, the phase detector generates an error signal. The error signal is filtered in the loop filter and fed back to the VCO to drive the VCO in a direction to eliminate the error signal.
The operation of a divider in a phase-locked loop is defined by the general equation: EQU f.sub.in =N.multidot.f.sub.out
where
f.sub.in is the input to the divider and the nominal frequency of the VCO PA1 N is the modulus of the divider by which f.sub.in is divided PA1 f.sub.out is the output of the divider and equals the fixed reference frequency due to feedback action. PA1 f.sub.in is the frequency of the input of the divider PA1 N=A.times.P+B.times.(P+1) PA1 N+1=(A-1)P+(B+1) (P+1) PA1 W =the radix of the rate multiplier, and PA1 Z =any number from 0 to (W-1) PA1 A=H-M-B PA1 B=L+P.times.H PA1 H=INT [N/P]=N(MOD P) PA1 M=INT [N/P(2P+1)-L/P +0.5], and PA1 L=N-P.times.H
To change f.sub.in and, hence, the frequency of the VCO, it is necessary to change N and/or the fixed reference frequency.
To change N, it has been the practice to use a programmable divider. The use of a programmable divider, however, is not suitable at high frequencies, e.g. when f.sub.in is greater than 80 mHz. This is because at high frequencies, the effective signal path lengths are too long and cause undesirable signal delays in the divider.
Another disadvantage of using a conventional programmable divider is that to obtain a fractional modulus N, complicated and cumbersome logic circuitry is typically required regardless of the frequency of f.sub.in. This is because a conventional programmable divider, e.g. counter, can only divide by an integer. Heretofore, this has severely restricted the availability of fractional modulus dividers.
In recent years, the frequency limitations of conventional programmable dividers have been overcome by the use of a prescaler between the VCO and the programmable divider.
One type of prescaler is a fixed divider which is specially designed to divide f.sub.in down to a frequency which is acceptable as an input to a conventional programmable divider, e.g. less than 80 mHz, without significant signal delays.
Another type of prescaler is a dual modulus prescaler which is specially designed to divide f.sub.in by either one of two values, e.g. P or (P+1), with no significant signal delays. In practice, the dual modulus prescalers are typically two fixed prescalers with switching circuitry used to preserve the low delays of the fixed prescalers. Such circuits, for example, are available from Motorola as Part No. 12009 (P=5); Part No. 12011 (P=8); and Part No. 12010 (P=10).
Another important consideration in the design of phase-locked loops concerns loop bandwidth. Loop bandwidth is directly proportional to the frequency of the reference oscillator and as a practical matter, the required bandwidth, i.e. loop response, should be less than 10% of the frequency of the reference oscillator. If it is greater than 10%, the loop becomes unstable, i.e. experiences excessive phase shift and gain loss through the phase detector due to time lag.